1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor integrated circuit, and more particularly, to a trench isolation method.
2. Description of the Related Art
Conventionally, LOCal Oxidation of Silicon (LOCOS) isolation technologies were widely used to provide electrical isolation in semiconductor integrated circuits. However, due to some drawbacks of conventional LOCOS isolation technologies, for example, a bird""s beak effect, alternative isolation processes were needed for isolating devices in high-density semiconductor integrated circuits. Trench isolation has been one of the various approaches being adopted to deal with the drawbacks of conventional LOCOS isolation technologies.
In trench isolation technologies, a trench region is typically formed by selectively etching a predetermined area of a semiconductor substrate. A dielectric layer for filling the trench region is formed over the entire surface of the resultant structure having the trench region. Next, an isolation trench is formed within the trench region by planarizing the dielectric layer by planarization processes such as chemical mechanical polishing (CMP). Here, if the trench region is narrow, the trench region is completely filled with the dielectric layer. However, if the trench region is wide, the trench region is typically over-etched during the CMP step, thereby causing dishing, i.e., the central portion of the isolation trench becomes thinner. Such dishing effect degrades the planarity of the semiconductor substrate having the isolation layer. In order to overcome the above-described drawback, many solutions have been proposed.
U.S. Pat. No. 5,372,968 discloses a method for improving the planarity of a wide trench region. However, in the method disclosed in U.S. Pat. No. 5,372,968, two steps are needed for forming trenches, that is, shallow trenches and deep trenches. Further, a spin-on-glass (SOG) layer must be etched back and removed. Such a method is complex and is difficult to attain high repeatability.
Accordingly, a need remains for an improved isolation method requiring fewer process steps.
It is, therefore, an objective of the present invention to provide a trench isolation method that can improve the planarity of a wide trench region by a simple process.
To achieve the above objective, the present invention includes the steps of forming a mask pattern which defines a first opening and a second opening wider than the first opening on a semiconductor substrate, forming a first spacer for filling the first opening and a second spacer at the side walls of the second opening, forming a sacrificial material layer pattern having an etching rate substantially equal to that of the semiconductor substrate in the second opening surrounded by the second spacer, exposing the semiconductor substrate under the first and second spacers by selectively removing the first and second spacers, simultaneously forming a deep trench region in the exposed semiconductor substrate and a shallow trench region in the semiconductor substrate under the sacrificial material layer by simultaneously etching the exposed semiconductor substrate and the sacrificial material layer pattern. Finally, an isolation layer is formed filling the deep trench region and the shallow trench region. The mask pattern is preferably formed by sequentially forming a pad oxide layer and a pad nitride layer on the semiconductor substrate, and patterning the pad nitride layer and the pad oxide layer.
The first and second spacer are preferably formed by forming a spacer material layer over the entire surface of the semiconductor substrate having the mask pattern, and anisotropically etching the spacer material layer until the top surface of the mask pattern is exposed. Here, the spacer material layer is preferably formed of a material layer having an etching selectivity against the mask pattern and the semiconductor substrate, and excellent step coverage. For example, in the case where the semiconductor is a silicon substrate and the mask pattern is formed of a silicon nitride layer, the spacer material layer is preferably formed a CVD silicon oxide layer. Also, the thickness of the spacer material layer must be at least half the width of the first opening. This is because the bottom of the first opening must be entirely covered by the first spacer.
The sacrificial material layer pattern is formed by forming a sacrificial material layer having an etching rate substantially equal to that of the semiconductor substrate, and planarizing the sacrificial material layer until the top surfaces of the mask pattern and the first and second spacers are exposed. Here, when the semiconductor substrate is a silicon substrate, the sacrificial material layer is preferably formed of one of a polysilicon layer, an amorphous silicon layer and a silicon oxynitride layer. Also, the sacrificial material layer is preferably thicker than the mask pattern, and the step of planarizing the sacrificial material is performed by CMP or etch back.
The first and second spacers are preferably removed by a wet etching process.
The shallow trench region and the deep trench region are formed by simultaneously etching the semiconductor substrate and the sacrificial material layer pattern having the substantially the same etch rate as the semiconductor substrate. Thus, the deep trench region is formed in the first opening, and both the deep trench region and the shallow trench region surrounded by the deep trench region are simultaneously formed in the second opening. As a result, a stepped trench region, in which the bottom of the central portion is higher than the bottoms of the edges, is formed in the second opening by a single-step etching process. Here, the sacrificial material layer pattern is completely removed while the trench region is formed. Therefore, an additional process step for removing the sacrificial material layer pattern is not required.
According to the present invention, a stepped trench region in which the bottom of the central portion is higher than the bottoms of the edges can be formed by a single-step etching process, and an additional process step for removing a sacrificial material layer pattern is not required. Therefore, the planarity of an isolation layer formed in a second opening can be improved by a simplified process.